Inhibit logic circuit



April 5, 196

Original Filed June 5, 1959 K. 0. KING ETAL.

INHIBIT LOGIC CIRCUIT 5 Sheets-Sheet l Q A B 8I=A'B'C' INVENTORS KENNETH0. KING' GEORGE F. MINKA BY Kw L44, THEIR ATTORNEYS April 5, 1966 K. 0.KING ETAL 3,244,902

INHIBIT LOGIC CIRCUIT Original Filed June 5, 1959 5 Sheets-Sheet 2 o 1 o0 1 1 1 1 1 1 0 Sum(Su)=A:B'C+ A'Bp'+AB'c'+ (ABC .1E .1) CurryGen(KQ)=ABC+ ABC+ABC'+ ABC (E .2)

.=)o= M lNVENTORS Q 11: Q 0 Q r 1 (c KENNETH 0. KING A B A B A B GEORGEF. MINKA THEIR ATTORNEYS April 5, 1966 K. 0. KING ETAL INHIBIT LOGICCIRCUIT 5 Sheets-Sheet 5 Original Filed June 5, 1959 \I \l 3 4 BA 3 0 Q.K a E E pm mm l J M w u u u u OF. H n n ma C NR B N0 A EE KG I n B A n un V .c n m B @m m B A c C 6 n Loki C @m A A 2 4. c c a o .o m u n S m Ic O w 6 r u C D 2 b S 9 3' B 8 B b 8 4 o 8 C 87 b8 l 8, w c [A o THEIRATTORNEYS United States Patent Ill Claims. (Cl. 307-458) Thisapplication is a division of patent application Serial No. 817,851,filed June 3, 1959.

This invention relates to means applicable, among other uses, to digitalprocessing and control systems, such as, for example, digital dataprocessors; and in which systems logical operations which may be definedin terms of Boolean algebra are performed upon information representedin binary signal form. More specifically, the invention relates tosystems of the characteristics noted, in which the logical operationsare performed by devices or elements capable of producing an output whencoerced from one physical state to another, and in which systems binaryinformation is stored in bistable devices. By the term bistable devicesis meant devices possessing two stable physical states.

Digital data processing and digital control systems which use bistablemagnetic cores as storage elements for storing information representedin binary signal form, are now well known in the art. The magnetic corestherein used are made of a material having an approximately rectangularhysteresis loop and having a sharply defined saturation flux value.Therein, also, a core is considered to be storing -a binary digit onewhen it is in a first of its two opposite remanent magnetic conditionsor states (commonly symbolically represented by 1), and to be storingbinary digit zero when it is in the second remanent state (commonlyrepresented by 0). Further, systems are known in which diodes are usedin performing logical operations upon binary information, and in whichbistable magnetic cores are employed as storage elements for storing theinformation. The reliability of diodes and such solid-state electronicdevices used in performing the logical operations, while presenting aconsiderable improvement over the previously used electrontube means, isnevertheless not as good as may be desired. Diodes, transistors, andlike devices are temperature-sensitive and have useful lifetimes whichare variable and dependent upon duty cycle, ambient temperature, etc.Accordingly, the reliability of the logical operations performed by, forexample, diode and magnetic core devices, is actually not much superiorto that attained when the operations are performed with the gene-rallyused diode logic circuit means. The present invention contemplatesperformance of logical operations by devices capable of being forced orcoerced to either of first and second physical states from the other andcapable of producing an output manifestation or signal when thus coercedfrom either such state to the other. In the exemplary illustrative em-'bodiment of apparatus according to the invention, bistable magneticdevices each comprising a magnetic core and associated windings 01'coils, are used as the only elements actually performing the logicaloperations. Such magnetic elements are readily coercible from either ofopposite stable magnetic states to the other, and when coerced cause anoutput potential to be produced in an output winding inductively linkedtthereto. And since such magnetic devices or elements operate withindefinitely long or permanent lifetime and within any temperature rangebetween 200 C. and 200 C. with practically 100% reliability, theinvention contemplates a rather considerable improvement in reliabilityof logic-perform 3,244,902 Patented Apr. 5, i966 ing circuitry. Further,by employing a novel type of logic which is hereinafter explained, theinvention permits a considerable reduction in the amount of hardware orcomponents that is required to mechanize a particular set of logicaloperations, while concurrently rendering much less critical the choiceof components, values of currents, and timing of operations. The noveltype of logic does, in fact, permit logical operations of all sorts tobe accomplished in a facile and practical mode by bistable magneticdevices of the type mentioned.

As previously indicated, the exemplary apparatus used to illustrate theprinciples of the invention uses as the logic-performing elements of anoperable logical system, two-state elements such as bistable magneticcores each having a respective set of windings. The set of windingsincludes at least one output winding in which an output signal isinduced whenever the core is flipped (that is, is caused to changestate), at least one power winding in which winding (or windings) thecoercing current (or currents) which effect recurrent change of state ofthe core course, and one or more inhibit windings which selectivelyconduct current (or do not conduct current) whereby the core is (or isnot) inhibited from being flipped by the coercing current or currents.In the exemplary apparatus, inhibiting coercive effort or force isprovided by current from one or more bistable devices of novelconstruction.

Herein, the two opposite states to which each twostate element isalternately coerced or driven are designated 0 and 1, respectively.Operations are conducted according to What is termed as two-phase mode.A first phase comprises a period wherein any two-state element may bechanged in state to produce an output signal (or inhibited to preventproduction of an output signal); and the second phase comprises a periodof time during which transient forces and signals in the system decayand during which preparations are made for an ensuing cycle ofoperations. The first phase is herein termed the write period, and thesecond phase is termed the read period, solely for definition purposes.In the exemplary apparatus herein described, the bistable magnetic coresmay be flipped from 0 to 1 during the write period and reversely flippedfrom 1 back to 0 during the read period. An output pulse of a firstpolarity is induced during the 0 to 1 flip, and a pulse of the oppositepolarity is induced during the return flip. While either output pulsecould be used, that pulse produced during the read period, that is,during the l to 0 flip, is selected for use. Also, in the exemplaryapparatus, all the cores are stressed toward the 0 state by a constantbias coercive force which is great enough to coerce any and all of thecores from 1 to 0 in the absence of a write clock. This coercive force,herein termed negative, is supplied by a constant bias current which ispassed through one set of drive windings including a winding for eachcore. In addition, each core is recurrently subjected to a positivecoercive force opposite to and of twice the strength of the bias, byrecurrent clock pulses which course through a second set of drivewindings. The clock pulses thus are of strength suflicient to overpowerthe bias and drive a core from 0 to 1. Thus the system of the exemplaryapparatus according to the invention prescribes that any core will beflipped from 0 to 1 by a clock pulse and reversely flipped from 1 to 0by the bias at the termination of the clock pulse, unless such action isprevented or inhibited by one or more negative coercive effects ofsufiicient strength to, when added to the bias, prevent flipping of thecore by the positive clock pulse. Flipping of cores from 0 to 1 occursduring the write period of a cycle, hence it is during the write periodthat logical operations will be cone3) sidered to be performed. Theoutputs produced by induction in an output or sense winding as a coreflips, during a read period, indicates the result of the logicaloperation or step performed, as will hereinafter be made fully evident.

Output or sense lines, each including one or moresense windings, serveas input lines to one or more of dual-input dual-output bistabledevices, whereby each such device is selectively caused to assume (or tcontinue to reside in) one or the other of its two stable states,dependent upon which input is energized by a sense line output of properpolarity. In this manner the binary result of the logical operation isstored in the device (or devices) and is represented by the particularstable state in which the device is left residing. The outputs of any ofsuch bistable devices are characterized by being currents, one or theother of which is flowing at any time, but, in general, not both flowingconcurrently. Such currents are used, in accord with principles of theinvention, to provide the mentioned preventing or inhibiting coerciveefforts, by being passed through inhibit windings on the proper cores.However, as will hereinafter be made evident, the currents may also beemployed for other control purposes. The currents accordingly are suchas to produce the required inhibiting or control forces.

In the exemplary apparatus illustrative of the principles of theinvention, the current outputs of the bistable devices are used torepresent the Boolean inverses or primes of Boolean terms orpropositions which are to be operated upon in accordance with statedlogical (Boolean) equations. These inverses or primes of terms orpropositions are selectively utilized in accord with principles of whatis herein termed inhibit core logic, to prevent the clock pulse of thenext cycle of operations from flipping to 1 the core or cores to whichthe respective proposition inverses are applied. It is important tonote, during this brief general description of characteristics of theinvention, that the power for driving the cores, and hence forperforming the logical operations, is not furnished by or suppliedthrough the currents rep-resenting inverses of the terms orpropositions. The necessary power is, rather, furnished by the clock andbias currents. By this .procedure the bistable devices or other circuitdevices which furnish the terms or propositions are relieved entirely ofthe burden of supplying power to the cores. When an inhibiting currentis flowing, there is no possibility of reversal of state of a corehaving a Wind-ing coursed by that current, hence no appreciable amountof energy is consumed from the currents in windings linked to the core.This is, in general, not true in the generally practiced type of corelogic, wherein the proposition signals are often called upon to supplythe power to reverse the state of a core.

Further, in accord with the invention, the logical and (logical product)function is generated for any number N of propositions, by using but onecore, that core having linked thereto respective windings for the clock,the bias, the sense line, and inhibit windings one for each respectiveone of the N propositions. As will be shown, several such productfunctions are readily summed by provision of windings and a single corefor each respective logical product, and a single sense line linked toall of the product cores. These features and characteristics, also, willhereinafter be fully explained in conjunction with a description of thepreferred exemplary physical means embodying the principles ofinvention.

It is, then, a principal object of the invention to provide meanssimpler than those heretofore known, for performing logical operationson information represented by binary signals.

Another object of the invention is to provide an improved mode forperforming logical operations or information represcnted by binarysignals.

Another object of the invention is to provide an improved bistable statedevice capable of furnishing directly the current for performing theinhibiting actions on magnetic core logical elements.

Another object of the invention is to provide a faster operating logicalsystem functioning in the inhibit core logic mode.

An additional object of the invention is to provide a fast-operatingsystem of exceptionally high reliability for performing logicaloperations upon binary signals.

Another object is to provide an improved type of logical circuitry forperforming logical operations upon binary signals.

Another object of the invention is to provide a new mode of producing asignal or manifestation representing the logical product of propositionsrepresented by respective signals.

Another object of the invention is to provide a novel mode formechanizing logical operations.

Another object of the invention is to provide simpler and moreeconomical mechanization of logical operations.

The foregoing objects and advantages of the invention, and othersthereof which will hereinafter be made apparent or become apparentthrough consideration of the following description and the appendedclaims, are anticipated or accomplished by the invention, a preferredillustrative physical embodiment of which is schematically depicted inthe accompanying drawings forming a part of this specification, and inwhich drawings:

FIGS. 1a and lb are diagrams illustrating special characteristics ofexemplary magnetic devices and of coercive forces used to operate themagnetic devices;

FIG. 10 is a set of waveform diagrams;

FIG. 1d is an explanatory diagram illustrating one type of magneticelement or core, and windings inductively linked thereto;

FIG. 1c is a symbolic diagram representing the core of FIG. 1d andappropriate signals;

FIGS. If and 1g are symbolic diagrams symbolically illustrating aparticular feature of the invention;

FIGS. 2a, 2b and 2c are symbolic diagrams in extension of those depictedin FIGS. 1 and lg, symbolically illustrating additional particularfeatures of the invention;

FIG. 3 is a set of diagrams illustrating how a simple digital computercomponent may be mechanized in accordance with principles of theinvention;

FIG. 4 is a diagram illustrating the electronic construction of a simpleexemplary serial adder according to principles of the invention, and theapplicable Boolean equations; and

FIG. 5 is a circuit diagram depicting a bistable device according to theinvention, as utilized in the adder schematically depicted in FIG. 4.

In certain respects and aspects this application presents improvementsupon the invention disclosed in co-pending application Serial No.615,279 of Ladimer J. Andrews et al., filed October 11, 1956 and now US.Patent No. 3,040,986.

Referring to the drawings, and first to FIG. 1a, the operation of anexemplary two-state logical element, in the form of a magnetic device orcore, as performed in accordance with the concepts of the presentinvention will be explained. The figure represents the so-called B-Hcurve, or cyclical magnetization loop, of a typical bistable magneticcore of well known type, and is a plot showing magnetic induction ormagnetization of the core under different degrees of both positive andnegative coercion effected by recurrently repeated applications ofcoercive effort by magnetic field of alternating polarities. Theordinates (B) of the plot are in units of magnetic induction, such asgausses; and the abscissae (H) in units of field strength, such asoersteds. Having once been magnetized substantially to saturation by anegative field, the core assumes a remanent state of magnetizationindicated by point m on the curve. Upon application of an increasingpositive coercive effort, the magnetization value progresses along theplot from point m successively to points 12, p and q, during whichprogress there is at first a relatively small change of magnetization toa point 11, followed by a relatively large change through point p topoint q, with only a small corresponding increase of applied positivefield or coercive effort. During the large change of magnetization fromm to q, the polarity of the magnetic device reverses and the device issaid to change state of fiip. Further increase in the applied positivefield drives the magnetization toward and possibly beyond a valueindicated at point r, at which point the core or device is substantiallysaturated in the magnetic sense. Thereafter, removal of the appliedfield or coercive effort results in the magnetization relaxing to aremanence value indicated by point s, which is comprised in the other ofthe two stable magnetic states in which the core can repose or reside inthe absence of any applied field.

The mentioned magnetic cycle is completed in a similar manner, withsuccessive application and removal of an oppositely directed (negative)magnetizing force or field (-H), during which correspondingmagnetization values I, u, v and w are reached, and the magnetizationrelaxing to the remanent state value indicated at m incident uponremoval of the magnetizing force or field. When the magnetization ispositive, as when at values such as q, r, s and t, the core or elementis herein considered to be in the 1 state; and when the magnetization isnegative, as exemplified at values n, m, v and w, the core is said to bein the 0 state. In the following explanation, the coercive effort orforce necessary to drive the magnetization from the value indicated at mto the value indicated at q, will be represented by the expression I;and similarly, the effort required to reversely coerce the core frommagnetization value s to value v will be designated by -I. In each casethe subsequent removal or disappearance of any applied coercive effortwill result in the core relaxing to a respective adjacent remanent statevalue, such as that of s or m. Vectorially, these two values of coerciveeffort or effect may be represented as indicated at the lower part ofFIG. 101, one being positive, and the other negative. Referring now toFIG. 1b which depicts a similar magnetization plot with an extension inthe application of negative coercive efforts, it is evident that if thecore were in the 0 state and a first coercive effort of +21 value wereconcurrently applied with a second effort of I value, the net effectwould be the same as the application of a single effort of value equalto +1, and the core would be driven to 1 and the magnetization wouldrelax to point s upon termination of the two coercive efforts. Ofcourse, if under the mentioned concurrent application of efiorts -I and+21 the core were already at state 1, no reversal of state would occur.

Considering further the diagram in FIG. 1b, it is evident that if anegative coercive force or efilort of --I value is continuously appliedto a core the magnetization will be changed from its normal remanencevalue, to a value such as that indicated at v. in effect, the remanencepoint will be shifted to point v and the core will be continuouslystressed with a negative coercive force while remaining in 0 state. Ifnow, with the continuous negative (I) coercive force still effective,the core is subjected to a positive coercive force of +21 value, themagnetization of the core will be shifted through values at points m, nand p, to that at point q. During this magnetization shift, the corewill be changed in state from 0 to 1 while still under stress of thenegative coercive (bias) effort. During continuance of the +21 force,the magnetization will be held at value q. Upon termination of the +21coercive force, the normal tendency of the core to relax to remanencepoints is augmented by the continuing negative bias, the latterreversely driv= ing the magnetization through points s, t and u to pointv. Thus the -I bias effort reverses the state of the core from 1 to 0.As previously noted, an output potential may be derived from a secondaryor output winding inductively linked to the core, at either or both ofthe changes of state. In the presently described exemplary apparatus,the steady negative bias (-1) is preferably (but not necessarily)continuously applied to all of a set of magnetic cores, and all of thecores of the set are recurrently subjected to a positive clockingcoercive effort of +2I value, whereby each core, unless otherwiseprevented or inhibited, is changed in state from 0 to 1 and thenreversely driven from 1 to 0. At any cycle of operation one or moreadditional coercive efforts of I value (or greater) may be added to thatof the continuous bias, and thus inhibit or prevent the core beingdriven from 0 to 1 by the +21 clocking effort. Three such additional orinhibiting efforts each of I value are vectorially represented as E1,E2, and E3 in FIG. 1b; and all or any of these efforts as well as thoseof the bias and the clock may be produced and applied to a core asindicated in FIG. 10!. In the latter figure, efforts E1, E2 and E3 areproduced by respective ones of currents A, B and C as indicated,supplied from a signal source PS5. The current or currents tending torecurrently drive the core 20 from 0 to 1 and back to 0 are supplied bya source PM.

FIG. 10 depicts wave forms and conditions of core 20 of FIG. 1d duringseven successive exemplary cycles of operation. The wave forms includethat of the clock pulses (which are not necessarily regularly recurringor periodic as shown), the Q or bias current, the three inhibitingcurrents, A, B and C, and a sense line output potential waveform. Thestates of the core at the various periods of the cycles are shown in thecore graph. Currents A, B and C are indicated as occurring or flowing atonly selected times. For example, A flows throughout only clock pulse 1,B during clock pulse 2, etc. Also these currents as well as the biascurrent are indicated as negative to indicate the negative magnetizationeffect relative to the positive clock current pulses. Actual polaritiesor directions of current flow depend upon the directions of therespective windings, as is well understood in the art. As the currentsare passed through the core windings of FIG. 1d, the following actionsoccur: at clock pulse 1, current A. (which when on may represent thetrue state of a proposition P1 and when off may represent the falsestate of the proposition) is flowing, hence the core is inhibited andremains in 0 state. During clock pulse 2, current B (representingproposition P is effective and the core is thus again inhibited frombeing driven to 1 by the clock pulse. During clock pulse 3, neither A, Bnor C (the latter representing a proposition P is flowing, and the clockpulse drives the core to l, as shown on the core graph. Upon terminationof clock pulse 3 the bias (Q) returns the core to O as indicated in thegraph. As the core is driven to 1 and returned to 0, respective ones ofpositive and negative potential pulses +VI and VI are generated in senseline S1, as indicated in waveform Vs below clock pulse 3. During clockpulse 4, current C inhibits change of state of the core and no senseline output appears. During each of clock pulses 5 and 6 neither of theinhibiting currents are active and the core is therefore flipped at eachpulse, with corresponding pairs of output potentials produced on thesense line, as indicated in waveform Vs.

In FIG. 1d the core 20 is represented as of toroidal form (although itmay be of rod-like or other form), and the windings for the clock pulsesCw and the bias and inhibiting currents are conventionally depicted asmultiple or partial turn coils. It will be understood that the inductivelinkages and number of turns may be other than as shown, dependent uponthe relative magnitudes of the currents, number of turns, structuralarrangement, etc., all selected in accord with known good circuit designprinciples. The particular structural arrangement shown is purelyexemplary and is used principally to aid in explaining the symbolic orshorthand representation of cores and windings as used, for example, inFIG. 1e, wherein the core 20 is represented by a circle, the +21 clockpulse Cw by the double-pointed upwardlydirected arrow, the -I bias (Q)and the -I currents A, B and C by respective single-pointeddownwardly-directed arrows, and the sense line by a horizontal line asin FIG. 1d. Thus the symbolic representation in FIG. le indicates thatan upwardly-directed arrow represents a current tending to coerce thecore to 1, and a downwardly directed arrow represents a current tendingto coerce the core in the opposite direction. The number of arrow pointson an arrow indicates at least approximately the relative strengths ofthe coercive efforts produced by the respective currents. The output orsense line, providing no appreciable coercive effect, is shown in aneutral (horizontal) attitude.

Further consideration of the previously explained matter and FIGS. 1dand 12 makes it clearly evident that with the clock current Cw and eachof currents A, B and C at zero value (inactive), the core is brought toby the bias, Q. Thereafter, when a clock pulse occurs with each of A, Band C inactive, the core is flipped (driven to l) and again flipped(returned to 0) by the clock pulse and the bias, and an output potentialis produced on the sense line at each flip. Also it is evident that ifany one, or all, or any combination, of A, B and C is active (currentflowing) the core will be inhibited and not flipped, and if the currentsA, B and C represented the previously mentioned Boolean propositions P Pand P no unobvious or useful operation would be performed.

As noted in the prior art literature, as in, for example, the paperentitled Pulse Switching Circuits Using Magnetic Cores by Karnaugh,published in the Proc. of the IRE, May 1955, at pages 570 through 583,it has heretofore been necessary to utilize a plurality of cores, withvery carefully proportioned windings and carefully regulated propositioncurrents which are accurately timed, if more than one proposition percore is to be acornmodated in a logical system using prior arttechniques and practices. Thus with the arrangement of FIG. 1d, whereinthe currents A, B and C were directly used to inhibit core 20, nounobvious result was secured. Therein, an output pulse would merelyindicate that neither of the propositions was present or active.However, if, in accord wtih the novel principles of the invention,currents A, B and C were made to represent the Boolean complements orprimes of the respective propositions, whereby absences of the currentswould represent the respective propositions, a very useful though subtleconcept is developed from which a large number of unobvious and veryuseful results flow directly or are readily attained. Since from FIG. 1dit is evident that the only time a sense line output is produced is whenall of the currents A, B and C are absent, a sense line output may beconsidered to represent the logical product (the and function) of theabsences or primes of the currents A, B and C. Thus by analogy it isevident that if the prime (absence) of an inhibiting current is used torepresent a true proposition, and presence of the current is used torepresent the inverse or false status of the proposition, logicalproducts of a plurality of propositions may be formed on a sense linewith but a single core. For example, in FIG. la, the structure depictedis such that a sense line output is the logical product of A, B and C,and. this is represented by the Boolean equation: S1=ABC shown in thelower part of the figure. Note that in this equation the clock (Cw) andthe bias (Q) have been omitted since they are, in this specific example,necessary in every operation and are understood to be present.

In computer and control procedures or operations conducted by logicaloperations according to the principles of Boolean algebra, it is usualfor both the true and false state signals (representing both the trueand false statuses of the propositions) to be made available. Forexample, a high voltage, or an active current, is utilized to representthe binary digit one (1) and a low voltage or absence of a current thenrepresents the inverse, binary digit zero (0). Each is the complement orinverse of the other. With this in mind, and thus denoting binarydigit-representing signals by respective alphabetical characters as wasthe case with Boolean propositions, an A, for example, may represent abinary one (and A then represents the complement, or binary zero), froma given source A of binary signals. With this notation, Booleanequations representing logical operations are readily derived, and theequations then mechanized or implemented with apparatus for performingthe represented operation. Hereinafter it is assumed that currentsrepresenting the true and the false states of a proposition areavailable, and in general, that when either is flowing or active theother is not flowing. Thus if current A is active current A is inactive(absent), and vice versa. In accord with the principles of the inventionif the logical product of A, B and. C is desired to be produced as asignal, S1, the equation is written: S1=ABC. To implement this equationusing the previously explained concept of inhibit core logic, a corewith windings for the complement currents or primes of A, B and C,namely, A, B and C, would be arranged in the fashion symbolicallyindicated in FIG. 1;. From that figure it is evident that when A and Band C are inactive or absent (that is, when A and B and C are active),an output will be produced on the sense line of core Ztla. This outputcan occur only when currents A and B and C are true or flowing, hencethe output signal Sll represents the logical product ABC. Note, however,that the core has no windings for currents A, B and C. With thissymbolic notation, it is easy to represent the mechanization of anyBoolean equation. For example, in FIG. 1g the equation Sl=LMNTUXrepresenting the logical product of the variables thereof, is mechanizedin the manner indicated in that figure by supplying to respectivewindings of core Ztlb currents representing the inverses or complementsof the variables of the equation. That is, the core has applied to awinding thereon a current L (the inverse of term L of the equation) anda current M (the inverse of term M of the equation), a current N(inverse of term N), etc., whereby the sense line output will occur onlywhen currents L, M, N, T, U, and X are all inactive, which is only whenall of proposition currents LMNTU and X are true (active). Note that thelatter currents, although possibly existing somewhere in an apparatus,are not applied to the core. All of the inhibiting currents are, ofcourse, of such value as to produce coercive effort of at least l value.

With the symbolic representation of FIGS. 1 and 1g in mind,mechanization or implementation of more complex Boolean equationsinvolving logical sums (or functions) will be shown to be an extremelysimple matter when the previously explained principles of inhibit corelogic are employed. In FIG. 2a, for example, an output signal will beproduced on the sense line Si when currents L, M and N linked to core200 are all absent (corresponding to L, M and N being true and active),or when currents L, S and T linked to core 255d are all absent(corresponding to L, S and T being true and active). Thus it is seenthat the Boolean equation SI:LMN+LST, representing the logical sum oftwo logical products, is satisfied by the two cores and windingsthereon; and it is made evident that to produce the logical sum oflogical terms it is only necessary to ap ply to respective cores thecomplements of the terms, and link to each of the cores a common senseline. The sense line output signal then represents the logical sum. Thisis further illustrated in HG. 2b, wherein the logical product LMN,implemented at core 2%, is summed with the logical product LST,implemented at core 20 to produce an output Sla when either or both ofthe logical products is produced. This logical sum of the two logicalproducts is represented in the first equation at the lower left in FIG.212. Also illustrated in FIG. 2b is the concurrent mechanization of thesecond (lower) equation in the figure, which requires the logicalsumming of the previously stated logical product LMN, with the logicalterm X. The logical product LMN is concurrently produced at core 2%(being produced on both of the sense lines Sit: and Slb), and thelogical term X is produced at core Ztlg. An output is produced on Slbwhen either or both of the terms of the equation is true. Thus it ismade evident that an output signal representing any stated Booleanequation may, using the principles of the invention, be readily andeconomically produced. It is understood, of course, that recurrentcoercive efforts capable of forcing the core or cores from 0 to 1 andreturn (such as the combined steady bias and the clock pulses), are inthe example contemporaneously applied to all the cores. While use of thebias is not essential, its creation is simple since it is merely aconstant current; and its use permits great latitude in the creation ofthe inhibiting currents. A single core may supply to each of a largenumber of sense lines an output signal representing the logical term orproduct implemented at that core, and a single sense line may be used toproduce a signal representing the logical (or) summation of all theproducts or terms represented by the respective cores to whichthe senseline is inductively linked.

An example of a less evident way in which somewhat more complex logicalfunctions may be mechanized is illustrated in FIG. 2c. In that figure,the double-strength positive clock effort is replaced by either ofprogram count number signals PCl, PCZ, P03, of a digital eomputer. Thesesignals are provided in the form of currents, only one of which can beeffective or active during a given cycle of operations. At any cyclewhen neither of the three is active, no output can be produced and theapparatus represented is considered to be idle. However, when any one ofthe three is active, an output may be produced, but will be producedonly if X and Y and Z are inactive. Thus it is evident that the core andwindings shown mechanizes the equation:

S1: (PC1+PC2+PC3) (XYZ) which is the logical product of the logical sumPC 1+PC2+PC3 with the logical product XYZ. rewritten:

which shows that logical sums may be obtained by use of only one core inthose cases wherein one variable is common to each term of a Booleanequation and wherein in each term there is a variable not common to anyother term. The figure i lustrates one way in which a PC number signalis produced. In that mode, an individual core C0, of a program-controlmatrix of cores, is selected and flipped by means not of this invention.Flipping of that core induces a sense line potential which triggers atransistor Tr, into conduction. The emitter-col- This equation may be'lector current passed through the transistor is conducted through adiode Di and through a winding on a core such as 20g. The sense linelinked to core C0 may also be inductively linked to other cores. Otherlike or similar circuit means, not shown, supply other PC signals; andit should be understood that more or fewer of the PC signals than thethree shown, may be used.

To further illustrate the technique of implementing or mechanizingoperational concepts according to the invention, the truth table, theBoolean equations derived therefrom, and an apparatus for mechanizationof the equations, all illustrative of a device for adding an ad dend Band a possible carry digit C, to an augend A, to provide a sum signal Suand a carry signal Ka, are depicted in FIG. 3. In the truth table thereare listed the eight possible different combinations of the true andfalse (one and zero) states of binary numbers A, B and C, and the sum Suthereof, and the carry digit Ka which will be true (a one) only when atleast two of A, B and C are ones. From the truth table the equations forthe sum Su (Eq. 1) and for the carry Ka (Eq. 2) are derived and are asshown below the truth table. It is evident from the truth table that thesum Su is true a one) when either of the second, third, fifth and eighthof the listed combinations of A, B and C occur; and the four terms ofthe sum equation:

define and represent the four alternative combinations either of whichmay produce a sum. Similarly in the case of the case o f the carry Ka,there is a carry (a one) if any of the fourth, sixth, seventh and eighthcombinations of A, B and C obtains; and the four expressions of Equation2 define and represent these conditions for a true or digit one value ofthe carry Ka. The inhibit core logic mechanizations of the respectiveequations for the sum SL4 and the carry Kn are directly derivable fromthe two equations themselves, and are symbolically illustrated orrepresented in the lower part of FIG. 3, it being important to rememberthat the symbolism used is the inhibit core logic mode previouslyexplained and in which the inverse of prime of the propositions definedby the Boolean equations, are applied to the cores. Thus in the equationfor the sum Su, the fourth (4) product term is ABC, corresponding toeach of A, B and C being a one; and this is mechanized at core 50a byinhibiting driving of that core to 1, by either or all of A, B and C(the inverses of A, B and C, respectively). In a similar manner, thethird term (3) of the equation for the sum Su is mechanized at core 5%,the second term (2) at core 590 and the first term, namely ABC, at core59d.

It is noted that the fourth product terms of both the sum equation andthe carry equation are identical, and so are enclosed in common bracketsin FIG. 3. Being identical, only one core is required for generating thefourth terms of both the sum output SH and the carry output Ka; and thuscore 5% is linked by both the sum sense line Stiy and the carry senseline 502:, saving one core. Since the remaining (first, second andthird) logical product terms summed in the carry (Ka) equation aredifferent from any logical product terms of the sum (S11) equation,separate cores 502, 50 and 50g are used in mechanizing those terms ofthe carry equation. Hence the carry sense line 50z is linked to core 50aand to each of cores 50c, 59 and Sdg to provide the carry signal Ka.

Now it is evident that there is required some means for supplyingcurrent signals for the inhibit windings. Means are necessary to supplyrespective signals representing the possible augends 0 and 1, thepossible addends 0 and l, and the possible carry 0 and 1. To meet therequirements of inhibit core logic as previously discussed in connectionwith FIGS. 1a, 1b, 1c and 1d, the signals must be in the form orcharacter of currents which may inhibit the change of state ofappropriate cores. In the present invention the means for providingsignals A, B and C, and the primes thereof, selectively, is in eachinstance a dual-input dual-output bistable-state circuit device similarin some respects to a bistable trigger circuit or flip-flop. This devicefurnishes a true output current signal on a true output line in responseto a true potential input signal applied to a true input line. Also thedevice has a complementary false input line for false input signalswhich are effective to trigger the device to the false state and providea false output current 1 1 signal on a corresponding false output line.The actual circuitry comprised in one of these bistable state devices isdepicted diagrammatically in FIG. 5.

In FIG. 5, 60 and 61 are alternately conductive transistorscross-connected as indicated to form a bistable circuit designatedgenerally by the symbol C. The transistors comprise respective bases60b, 61b, respective emitters 60c, 61c, and respective collectors 60c,61c. The collectors are connected to respective junctions 62, 63; andcross-connections from respective ones of these junctions to the base ofthe opposite transistor are made through coupling networks comprisingresistor R2, capacitor C2, and resistor R3, capacitor C3, respectively,as indicated. A special biasing current path through R2 and junction 62includes resistor R6 connected to a positive power supply pole orterminal +42, and a resistor R8 connected between junction 62 and anegative power supply pole 50. Similarly, a complementary current pathis provided through R5, R3 and R7, as indicated.

Thus respective currents normally flow through respective paths +42, R6,R2, 62, R8, 50, and +42, R5, R3, 63, R7, 50, and one of the transistorsis conductive and the other is as a result biased to nonconductivestate, or off. Assuming that transistor 60 is made conductive, as byapplication of a negative potential pulse to its base 6%, junction 62will be brought to ground potential, and junction 63 will be at about-12 units (volts, for example), due to the current from +42 throughresistors R5, R3 and R7. With the potential at junction 62 thus raisedfrom -12 to ground potential, transistor 61 is securely biased off anddiode 64 is forward biased into conduction and current flows from groundthrough the emitter-collector circuit of junction 62, transistor 60,junction 62, diode 6d and the load interest of simplicity. Obviously,triggering potentials may be secured from sources other than sense lineslinked to cores, since any source of negative-going pulses is sutiicientfor the purpose.

Thus it is evident that with either of the transistors 60 and 61conductive, a negative-going triggering pulse applied to the inputterminal of the opposite transistor circuit will change the conductivestate of the device Q, in a manner similar to that evidenced in anordinary bistable trigger circuit or flip-flop. Further, the bistablecircuit means or device, depicted in the dash-line rectangle BSD in FIG.5, thus provides, through the current conducted through transistor 60and diode 64 (or, alternatively, that conducted through transistor 61and diode 65), a current which may be employed as the prime of aproposition to inhibit reversal of state of as many magnetic cores asthe respective output line is inductively linked to; and this withoutthe necessity for the current to provide any power for reversing thestate of any core. As depicted in FIG. 5, diode 64 is interposed in aline 60z connecting junction 62 to the negative (-8) power source poleor terminal through inhibit windings on cores 52 and 53 to each of whichcores a sense line Ss is inductively linked. Similarly transistor 61 anddiode 65 may pass current via a line 61z through inhibit windings oncores 51 and 54 to each of which a sense line Sc is linked. It will benoted that, since when the current or signal C (or C) is flowing in anoutput line, no core to which that line is linked can be circuit to a -8terminal of a power supply. In this example the load comprisesrespective inhibit windings 521, 53i on cores 52, 53, respectively, anda current limiting resistor R10. It is evident that if, under thesecondition, a false trigger pulse 0 of negative polarity is applied atthe false input terminal 611' of the device as indicated, a very smallbase-current of very low power requirement will flow in transistor 61,and the latter will thereby be triggered into conduction. As conductionin creases, the potential at junction 63 increases from 12 to groundpotential and that positive-going potential is applied through resistorR3 to the base 60b of transistor 60 and serves to bias the latter tocut-oft. Thus there is imposed upon the input or triggering pulse only avery low power requirement, the current through the transistorfurnishing the cut-oil power. In the exemplary device according to theinvention the trigger input potential is the potential induced in asense line as a core is reversed in state. For example the true triggersignal or input, c, for bistable device Q is generated upon a sense line60s linked to a core as indicated in FIG. 5. Similarly the false inputsignal, c, to device Q is generated on a sense line 61s linked to eachof cores 56 and 57. Since only a very low-power pulse is required totrigger either of transistors 60 and 61, very little power is requiredto be furnished by the core or cores linked to the respective triggersense line. While cores 55, 56 and 57 have other windings thereon, suchother windings are here omitted in the reversed in state and there canbe no back voltage induced in that line. Also, conversely, when a core,such as 51, 52, 53 or 54, is driven to 1 state and back voltage isinduced in the respective drive winding or line, there is no currentflowing in the line (since the respective diode, 64 or 65 as the casemay be, is back biased against conduction). Hence the diodes serve asbutters and prevent output load fluctuations and noise potentials fromaffecting the stability of the device Q in either of its two states.

While in the presently explained illustrative embodiment of a bistablesignal device according to the invention, the true and false outputsignals are currents, the bistable-state device Q depicted in FIG. 5 canas well be employed to provide true and false potential output signalsin the event that is desirable. These potential signals are derivedacross respective ones of resistors R10 and R9, as indicated by therespective arrow connections C and C to the lower ends of respectiveones of those resistors. This is distinctively different from the usualflip-flop output signals, which would be derived as potentials atjunctions 62 and 63 as indicated by the brokenarrow connections at thosepoints and would thus subject the bistable state device to possibilityof unwanted triggering by load fluctuations or noise potentials. Andwhile in FIG. 5 the connections for the output currents or signals C andC are shown as each linking two cores, it is clear that any number ofcores may be so linked and effectively inhibited from changing state byeither of the respective inhibit signals. Since no power need hesupplied by the inhibiting current, there is no possiblity ofoverloading the relatively simple power supply means needed to supplythe current. When one of the input signal cores, such as 55, 56 or 57,is driven from 0 to l and returned to 0, both positive and negativepulses are produced on the sense line and applied to a transistor baseThe positive-going pulse merely further biases the transistor off, andonly the negative-going pulse is eflective to trigger the bistabledevice. Such is the operation in the specific circuit shown; however, ifNPN transistors were used, or the direction of the sense winding werereversed, the pulse produced as the core is driven from 0 to 1 could beused for triggering. In exceptional cases this expedient may be used,but generally triggering will be eifected as the core is returned from 1to 0.

In FIG. 4 there is diagrammatically illustrated a computer component inthe form of a serial binary adder composed as an exemplary structureaccording to the principles of the invention, and arranged to performthe addition operations as defined in FIG. 3. In this exemplary computercomponent chosen to illustrate the practical application of theprinciples of the invention, binary signals representing an augend aresupplied by a signal means 8t), and similar signals representing anaddend are supplied by a means 81. The signals are negative-goingpotentials, those representing the digit one appearing on line 32a. forthe augend, and on line $311 for the addend, and those representingdigit zero appearing on lines 82b and 83 as indicated by the labels.Both of the signal means 8t) and 81 may be controlled by clock signalsfrom a clock 84 as indicated. The clock supplies pulses of the nature ofthose illustrated in FIG. 10. The input digital augend and addendsignals are supplied to respective bistable state devices, A and 2 eachof which is of the type previously explained in connection with FIG. 5,and which devices are used to store the augend and addend input digitsduring a cycle of operations. The arrangement is such that signalsrepresenting digit zero will be applied via line 82b (or 83b) as thesignal a (or ,b) to the off or false input terminal of the respectivedevice A (or B), and thus trigger the device to the false state andcause an output current to flow in line S'I' (signal A) or in line 89(signal B), as the case may be. Similarly, a signal from 80 (or 81)representing the digit one, will be applied on a respective line 82a (or83a) as the true input a, to device A (or as the true input b, to device12), as the case may be. Accordingly, device A will selectively supplycurrent on either of output lines 86x, 872, the currents being termedsignals A and A, respectively, and each being of coercive value at leastsufficient to inhibit change from O to 1 of any core to which therespective output line is linked. Similarly, the currents selectivelysupplied by device 11 are termed B and B, and are of at least I coercivevalue. The adder includes the aforedescribed device Q as the means fortemporarily storing and supplying the carry signal, C or C (carry one orcarry zero, respectively) to the logic-performing cores and windings.

In FIG. 4 the respective cores of the adder are shown as verticallydisposed slim rectangles, each numbered as indicated in a circle at theupper end thereof. Windings on a core are indicated by slant-lines atintersections of the core with respective selected output current lineswhich are shown as horizontal lines. For example, core 51 has a windingfor clock signal Cw (double slant line at the intersection of the clockpulse and the core), a winding for bias signal Q, an individual windingfor each of currents AQB and C, and a sense winding connected in senseline Ss on which is generated the sum signal Su. The other'cor-es havewindings as indicated. The directions of the various signal currents areindicated by arrow points in the respective linesat the left of core 51.The convention or symbolism employed in FIG. 4 is similar to thatdiscussed to some extent in the aforementioned paper by Karnaugh and nowWell known in the art as the mirror notation, wherein if the slant-linerepresenting a winding were a mirror and the current in the current linewere a beam of light traveling in the same direction as the current, thelight would be reflected either upwardly (l) or downwardly (0) accordingto the direction of the slant line; and the interpretation is that ifthe light were thus reflected upwardly the current would tend to coercethe core in the direction of the 1 state and if it were reflecteddownwardly the current would tend to coerce the core to 0. Thus in FIG.4 the upper ends of the cores are as a group labeled 1 and the lowerends are similarly labeled-O. On current-carrying windings, double slantlines indicate the aforedescribed 21 (double strength) coercive effort,and single slant lines denote 11 coercive effect or effort, withpossible exceptions and modifications as hereinafter noted. Thus theclock sig nal Cw is applied with 21 positive (upward) effect and thebias (Q) continually exerts a negative coercive effort of value Itending to drive or hold the cores to 0. Signals cated. For example,current A is applied to each of cores *51, .52 and 56. A clear signal of11 effect or greater is normally continuously applied and is effectiveon only core 57. Three sense lines, Ss, 60s and 61s are linked bywindings to cores as indicated, and it is in these lines that signalsrepresenting the sum SM, the one carry, and the zero carry, aregenerated when certain cores are flipped as a result of having not beeninhibited.

The cores and windings arrangement in FIG. 4 is the physical embodimentor mechanization of the Boolean equations (Eq. 1, Eq. 3, and Eq. 4) setout at the lower part of the figures. The reason for substituting Eqs. 3and 4 for Eq. 2 of FIG. 3 will hereinafter be explained. Each of theterms of the equations is assigned an individual core. As indicated bythe corresponding numerals in circles above the terms of the equationsin FIG. 4, the first term of Eq. 1 is mechanized by or upon core 51, thesecond term is mechanized by core 52, etc. For example, the first sumterm (derived from line 2 of the truth table in FlG. 3) is ABC.Remembering that in applyiug inhibiting currents to the cores in accordwith the previously explained principles of inhibit core logic, theinverses of the terms are actually applied as inhibiting curents, it isnoted that core 51 has windings for application thereto of signalcurrents A, B and C (the inverses of the first term of Eq. 1). Thus whenthe signal from source 3:) representing the digit zero is applied to thefalse or n input side of device A via line 82b, the device is triggeredto produce a current output (A) on lead ii7z. Lead 87z is coupled tocores 53, 54 and 55, which are thereby inhibited by signal A. Similarly,in the case of the digit zero signal from source 81, the signal isapplied via 33b to the Z2 input line of device B and the latter will betriggered to produce a B output current signal on lead 8%. Lead 89z haswindings coupled to cores 52, 54 and 55, which are thereby inhibited. Aone carry is represented in the first term of Eq. 1, hence device Q willbe producing an output C as a current on line 60z, and cores 52 and 53are thereby inhibited. Thus at any cycle of the adder at which A is azero, B is a zero, and the carry is a one, each of cores 52, 53, 54 and55 is inhibited (together with core 57 which is normally inhibited bythe steady clear signal). Cores 51 and 56, however, are not inhibited,and will be flipped by the next clock pulse Cw and the bias Q at thetermination of the clock pulse. Thus at the termination of the clockpulse a negativegoing pulse is generated on sense line Ss, indicating aone sum signal Su, and a similar pulse is generated on sense line 61s,triggering device Q to the false state to generate a C (carry digitzero) signal. Thus the logical product AB'C, the first term of Eq. 1,has been shown to be produced in response to the input signals toprovide the desired and expected addition of B (O) and C (l) to A (0) toget a sum Su of one and a zero'carry. The other possible combinations ofA, B and C, as listed in the truth table, may similarly be tested andfound to yield correct sum and carry outputs on lines Ss, 61s and 69s.

In the sum and carry equations set up in FIG. 3, as developed from thetruth table, there were four terms in each equation, one of the termsbeing common to both the sum and carry. While the mechanization of theadder could follow the representation at the lower part of FIG. 3 andinclude seven cores to produce all the terms, a comparison of the Csignal (truth table, fourth column) with the generated carry signal Kain the sixth column, shows that the two differ for only two of the eightpossible combinations of inputs. That is, they differ only for thesecond and seventh of the combinations. In the second combination, thechange of the carry, Ka, relative to C is from 1 to 0, and this isindicated in the next-to-last column of the truth table. In the seventhcombination, the change of Kn relative to C is from 0 to l, as indicatedin the last column of the table. Thus the output (and hence the state)of the Q device does not require to be changed except when A and B areboth zero (second combination), and when A and B are both one (seventhcombination). Accordingly, rather than use seven cores to mechanize Eqs.1 and 2, saving of one core can be elfected by using one core to changedevice 3 from true to false (C to C) and one core to change the devicefrom false to true (C to C). Equations 3 and 4 (FIG. 4) show that thetrue trigger input 0 to device Q, necessary to change from C to C(corresponding to the seventh combination) is produced by flipping ofcore 55 when digit A and digit B are both one. In inhibit core logic,this means that the core should be flipped when both of current signalsA and B are zero and current signals A and B are in effect. Hence core55 bears windings for and B and can be flipped only when both of thelatter signals are zero and thus only when currents A and B areetfective. Core 55 also has a clock winding of 21 effect, a bias (Q)winding, and a sense line winding connected in line 6%, so device Q istriggered true by an output potential produced on sense line dds whencurrents A and B are both flowing (the inverse of A and B each beingzero). A similar mechanization of Eq. 4 on core 56 requires windings forthe clock, bias, A, and B; and a sense winding connected in the false C)input line dis of device Q, whereby the device is triggered to producesignal current C (no carry) whenever A and B are both false.

Thus the apparatus portrayed in FIG. 4 is effective to add to successiveaugends the corresponding successive addends and to store and add anynext-previously created carry digit. At the termination of the serialaddition of the binary digits of multi-digit numbers, the carry-storagedevice, Q, may be reset to zero by any suitable mode and means. In theexemplary adder of FIG. 4, device Q is easily reset or cleared byopening the clear switch to interrupt the normally active current in theclear line, thus permitting core 57 to be flipped. Core 5'7 has a sensewinding connected in sense line 61s and hence the latter will be pulsedwhen core- 57 is flipped, and thus device Q will for certain he broughtto the false state if not already in that condition. The clear term inthe false triggering input equation (Eq. 4) for device Q is mechanizedby core 57.

From the preceding description it is evident that the novel bistabledevice, such as device Q, requires but a very small power input totrigger it to either state from the other of its two stable states, andin either state supplies a current representative of that state andeminently suitable for inhibiting the driving of cores by the clock (Cw)pulses. Also it is noted that the device is such that baclcwardlygenerated potentials in an output line of the device can have no adverseeffects on the device itself because of the blocking effect of the diode(64 or 65 in device Q). While in the illustrative embodiment ofapparatus no back voltage of any appreciable magnitude can be induced bycore windings because no core can reverse in state while an outputcurrent flows in a winding linked to the core, nevertheless in sometypes of apparatus such potentials can present serious problemsnecessitating special buffer amplifier stages in the output circuits.Further, it is evident that one or more sense lines, each linked to oneor more cores, may be used directly for providing the very low-powertriggering pulses needed to trigger the device from one state to theother, and also it is evident that since only a small amount oftriggering power is required, relatively small cores may be employed. Asnoted, too, the bistable state device Q may also supply true and falsepotential outputs either with, or without, used current outputs.

Also it is evident from the description of the mode of operation of theapparatus using the principles of inhibit core logic, that the matter oftime-coincidence and relative magnitudes of proposition signals is notat all critical, the only essential being that the inhibit signalsattain inhibiting value prior to commencement of the clock pulse andmaintain that value until after the clock pulse decays. Further, themagnitudes of the inhibit signals may be much greater than is necessaryfor core inhibiting, without adverse effect. in fact, as is indicated inFIG. 1b, the shuttle potentials induced in core windings are reducedwhen the negative inhibit signals are of greater than if eifect, sincethe core then operates farther out along the saturation limb of the 8-Hdiagram. The shuttle voltages involved due to the slight change (b) ofmagnetization when one or two, or more, inhibiting currents becomeeifective, are shown by FIG. 1b to decrease markedly as the number and/or magnitude of inhibiting currents increases. Since the amplitudes ofany or all of the inhibiting currents can safely be such as to produceconsiderably more than 11 coercive effect for each such current, theselection of circuit hardware and power supplies is much less criticalthan is usual in logical circuitry.

Additionally it will be evident that by using what is herein termedinhibit core logic it is possible to mechanize a logical product of Npropositions with a single core and without the necessity for precisecontrol of current amplitudes nor precise control of coincidence ofsignals. The bistable state devices are triggered to change state duringthe read period, that is, during the interval between the fall of theclock pulse and commencement of the next succeeding clock pulse.Actually, the bistable state device, such as A, E and Q, changes statenearly instantly after the logical operation is performed by the coreasit flips but the substantially contemporaneous change in the outputsignal cannot change the performed operation; and this allows plenty oftime for the aforedescribed lowpower triggering of a device in twostages to occur.

The preceding description of a practical embodiment of apparatusaccording to the concepts and principles of the invention demonstrateattainment of the aforestated objects of the invention. In the light ofthe present disclosure it will be evident to those skilled in the artthat the invention provides a new and powerful technique formechanization of logical digital processes, and a simple means thereforwhich is eminently adapted to simple and easy maintenance procedures andwhich in fact requires much less maintenance of logical elements than isusual in logical circuitry. The invention provides a simple way ofperforming inhibit core logic in a twophase cycle with a minimum ofapparatus and utilization of currents which are not critical. Cores arenot required to serve as transformers to furnish power to flip othercores, and thus selection of cores is noncritical. The inhibitingcurrents, being not required to furnish power to flip cores, areproducible by noncritical means; and the bistable state deviceseifective to produce such currents are simple and well-protected againstbeing triggered by noise potentials generated in inhibit windings.Further, the bistable state device disclosed is such as to require apractically negligible amount of input power for initially triggeringthe device for initiating a change from either state to the other, sincethe power needed to bias the presently conductive transistor to cut-offis supplied by the initial current surge through the oppositetransistor. In the light of the disclosure changes and modifications areevident to those skilled in the art, hence it is not desired to limitthe invention to the specific exemplary mode and apparatus described.

What is claimed is:

it. Apparatus for translating binary input signals supplied aspotentials on respective first and second input signal lines, intocorresponding \binary output currentsignals on corresponding first andsecond output signal lines, said apparatus being electricallysymmetrical and comprising: first and second transistors; first andsecond potential dividers each comprising first, second and thirdresistors and each having a first junction between its first and secondresistors and a second junction between its second and third resistors;means for energizing said potential dividers to provide thereacross apotential diiference including positive and negative potentials withrespect to a neutral potential; first and second diode means; first andsecond current-circuit means providing respective output signal linesfor alternatively supplying either of first and second current-signalsserially through a respective transistor and through a respective firstjunction and through a respective diode and through a respective outputsignal line; and first and second trigger circuit means each connectedto a trigger element of a respective transistor and to a respectivetrigger input line and to the second junction of the opposite potentialdivider, whereby application of a triggering potential on either one ofsaid trigger input lines triggers into conduction the respectivetransistor and permits current flow therethrough to thereby bring therespective first junction to said neutral potential and thereby bias theopposite transistor to nonconductive state and thereby selectivelyprovide an output current-signal on but one of said output lines at atime and selectively as determined by application of a triggerpotential.

2. In apparatus for performing logical operations and including at leastone bistable magnetic core coercible from either of its states to theother and having a power winding, at least one inhibiting winding and anoutput winding coupled thereto, said apparatus also including means forapplying a power signal to said power winding -for switching said coreunless inhibited by :an inhibiting signal applied to said inhibitingwinding, the improvement comprising transistor circuit means responsiveto output signals induced in said output winding (for providing aninhibiting signal for application to said inhibiting winding, saidtransistor circuit means comprising: first and second transistors eachcomprising a base, an emitter and a collector, means coupling saidoutput winding to the base of said first transistor, means coupling thecollector of said first transistor to the base of said second transistorand the collector of said second transistor to the base of said firsttransistor so as to provide [for bistable operation of said circuitmeans in response to the signal induced in said out-put winding as aresult of the switching of said core, a diode, and means coupling thecollector of one of said transistors to said inhibiting winding throughsaid diode, said diode being poled in a direction so as to permit theinhibiting signal to be applied from said circuit means to saidinhibiting winding while isolating said circuit means from signalsinduced in said core except via said output winding.

3. In apparatus for penforming logical operations and including at leastone bistable magnetic core coercible fl'OIll either of its states to theother and having a power winding, at least one inhibiting winding and anoutput winding coupled thereto, said apparatus also including means forapplying -a power signal to said power winding for switching said coreunless inhibited by an inhibiting signal applied to said inhibitingwinding, the improvement comprising transistor circuit means responsiveto output signals induced in'said output winding for providing aninhibiting signal for application to said inhibiting winding, saidtransistor circuit means comprising: first and second transistors, meanscoupling said output winding to the input of one of said transistors,means interconnecting said transistors for bistable operation inresponse to the signal induced in said output winding as a result of theswitching of said core, a diode, and means coupling the output of one ofsaid transistors to said inhibiting winding through said diode, saiddiode being poled in a direction so as to permit the inhibiting signalto be applied from said circuit means to said inhibiting winding whileisolating said circuit means from signals induced in said core exceptvia said output winding.

4. In apparatus for penforming logical operations and including at leastone bistable magnetic core coercible from either of its states to theother and having a power winding, at least one inhibiting winding and anoutput winding coupled thereto, said apparatus also including means forapplying a power signal to said power winding for switching said coreunless inhibited by an inhibiting signal applied to said inhibitingWinding, the improvement comprising transistor circuit means responsiveto output signals induced in said output winding [for providing aninhibiting signal for application to said inhibiting winding, saidtransistor circuit means comprising: first and second transistors eachcomprising a base, an emitter and a collector, means coupling saidoutput winding to the base of said first transistor, means coupling thecollector of said first transistor to the base of said second transistorand the collector of said second transistor to the base of said firsttransistor so as to provide for bistable operation of said circuit meansin response to the signal induced in said output winding as a result ofthe switching of said core, a load impedance means, a diode coupled tothe collector of one of said transistors, and means coupling saidinhibiting winding between said load impedance means and said diode,said diode being poled in the direction of inhibit current flow.

5. In apparatus for performing logical operations and including at leastone bistable magnetic core coercible from either of its states to theother and having a power winding, at least one inhibiting winding and anoutput winding coupled thereto, said apparatus also including means forapplying a power signal to said power winding for switching said coreunless inhibited by an in hibiting signal applied to said inhibitingwinding, the improvement comprising transistor circuit means responsiveto output signals induced in said output winding for providing aninhibitive signal for application to said inhibiting winding, saidtransistor circuit means comprising: first and second transistors eachcomprising a base, an emitter and a collector, means including first andsecond impedance means and first and second voltage sources for couplingthe collector of said first transistor to the base of said secondtransistor and the collector of said second transistor to the base ofsaid first transistor so as to provide for bistable operation of saidcircuit means in response to the signal induced in said output windingas a result of the switching of said core, a third impedance means, athird voltage source connected to one end of said third impedance means,a diode, and means coupling one end of said inhibiting winding to theother end of said third impedance means and the other end of saidinhibiting winding to the collector of one of said transistors throughsaid diode, said diode being poled in the direction of inhibit currentflow.

6. In apparatus for performing logical operations and including aplurality of bistable magnetic cores each coercible from either of itsstates to the other and each having a power winding, at least oneinhibiting winding and an output winding coupled thereto, said apparatusalso including means for applying a power signal to each power windingfor switching each core unless inhibited by an inhibiting signal appliedto its respective inhibiting winding, the improvement comprisingtransistor circuit means responsive to output signals induced in theoutput winding of at least one of said cores for providing at least oneinhibiting signal for application to the inhibiting winding of at leastone of said cores, said transistor circuit means comprising: first andsecond transistors, means coupling the output winding of at least one ofsaid cores to to input of one of said transistors, means coupling theoutput Winding of at least another one of said cores to the input of theother of said transistors, means interconnecting said transistors forbistable operation in response to the output signals applied to saidinputs, first and second diodes, means coupling the output of one ofsaid transistors to the inhibit winding of at least one of said coresthrough said first diode, and means coupling the output of the other ofsaid transistor to the inhibit winding of at least another of said coresthrough said second diode, each of said diodes being poled in thedirection of inhibit current flow.

'7. In apparatus for performing logical operations and including aplurality of bistable magentic cores each coercible from either of itsstates to the other and each having a power winding, at least oneinhibiting winding and an output winding coupled thereto, said apparatusalso including means for applying a power signal to each power windingfor switching each core unless inhibited by an inhibiting signal appliedto its respective inhibiting winding, the improvement comprisingtransistor circuit means responsive to output Signals induced in theoutput winding of at least one of said cores for providing at least oneof inhibiting signal for application to the inhibiting winding of atleast one of said cores, said transistor circuit means comprising: firstand second transistors, each of said transistors including a base, anemitter and a collector, means coupling the output winding of at leastone of said cores to the base of one of said transistors, means couplingthe output winding of at least another of said cores to the base of theother of said transistors, means interconnecting said transistors forbistable operation in response to the output signals applied to saidbases, first and second diodes, means coupling the output of one of saidtransistors to the inhibit winding of at least one of said cores throughsaid first diode, and means coupling the output of the other of saidtransistors to the inhibit winding of at least another or" said coresthrough said second diode, each of said diodes being poled in thedirection of inhibit current flow.

8. In apparatus for performing logical operations and including aplurality of bistable magnetic cores each coercible from either of itsstates to the other and each having a power winding, at least oneinhibiting winding and an output Winding coupled thereto, said apparatusalso including means for applying a power signal to each power windingfor switching each core unless inhibited by an inhibiting signal appliedto its respective inhibiting winding, the improvement comprisingtransistor circuit means responsive to output signals induced in theoutput Winding of at least one of said cores for providing at least oneinhibiting signal for application to the inhibiting winding of at leastone of said cores, said transistor circuit means comprising: first andsecond transistors, each of said transistors including a base, anemitter and a collector, means coupling the output winding of at leastone of said cores to the base of one of said transistors, means couplingthe output Winding of at least another of said cores to the base of theother of said transistors, means coupling the collector of said firsttransistor to the base of said second transistor and the collector ofsaid second transistor to the base of said first transistor so as toprovide for bistable operation of said circuit means in response to theoutput signals applied to said bases, first and second diodes, meanscoupling the output of one of said transistors to the inhibit Winding ofat least one of said cores through said first diode, and means couplingthe output of the other of said transistors to the inhibit Winding of atleast another of said cores through said second diode, each of saiddiodes being poled in the direction of inhibit current flow.

9. In apparatus for performing logical operations and including aplurality of bistable magnetic cores each eoercible from either of itsstates to the other and each having a power winding, at least oneinhibiting Winding and an output Winding coupled thereto, said apparatusalso including means for applying a power signal to each power windingfor switching each core unless inhibited by an inhibiting signal appliedto its respective inhibiting winding, the improvement comprisingtransistor circuit means responsive to output signals induced in theoutput winding of at least one of said cores for providing at least oneinhibiting signal for application to the inhibiting winding of at leastone of said cores, said transistor circuit means comprising: first andsecond transistors, means including first and second impedance means andfirst and second voltage sources "for coupling the collector of saidfirst transistor to the base of said second transistor and the collectorof said second transistor to the base of said first transistor so as toprovide for bistable operation of said circuit means in response to thesignal induced in said output windings applied to said bases, third andfourth impedance means, third and fourth voltage sources, meansconnecting said third voltage source to one end of said third impedancemeans, means connecting said fourth voltage source to one end of saidfourth impedance means, means coupling one end of an inhibiting Windingto the other end of said third impedance means and the other end of theinhibiting winding to the collector of one of said transistors throughone of said diodes, and means coupling one end of another inhibitingWinding to the other end of said fourth impedance means and the otherend of said another inhibiting winding to the collector of the other ofsaid transistors through the other of said diodes, said diodes beingpoled in the direction of inhibit current flow.

10. The invention in accordance with claim 9, Wherein means are providedcoupled to the ends of said third and fourth impedance means which areopposite from the ends coupled to said third and fourth voltage sourcesfor providing binary voltage output signals.

I No references cited.

IRVING L. SRAGOW, Primary Examiner.

4. IN APPARATUS FOR PERFORMING LOGICAL OPERATIONS AND INCLUDING AT LEASTONE BISTABLE MAGNETIC CORE COERCIBLE FROM EITHER OF ITS STATES TO THEOTHER AND HAVING A POWER WINDING, AT LEAST ONE INHIBITING WINDING AND ANOUTPUT WINDING COUPLED THERETO, SAID APPARATUS ALSO INCLUDING MEANS FORAPPLYING A POWER SIGNAL TO SAID POWER WINDING FOR SWITCHING SAID COREUNLESS INHIBITED BY AN INHIBITING SIGNAL APPLIED TO SAID INHIBITTINGWINDING, THE IMPROVEMENT COMPRISING TRANSISTOR CIRCUIT MEANS RESPONSIVETO OUTPUT SIGNALS INDUCED IN SAID OUTPUT WINDING FOR PROVIDING ANINHIBITING SIGNAL FOR APPLICATION TO SAID INHIBITING WINDING, SAIDTRANSISTOR CIRCUIT MEANS COMPRISING: FIRST AND SECOND TRANSISTORS EACHCOMPRISING A BASE, AN EMITTER AND A COLLECTOR, MEANS COUPLING SAIDOUTPUT WINDING TO THE BASE OF SAID FIRST TRANSISTOR, MEANS COUPLING THECOLLECTOR OF SAID FIRST TRANSISTOR TO THE BASE OF SAID SECOND TRANSISTORAND THE COLLECTOR OF SAID SECOND TRANSISTOR TO THE BASE OF SAID FIRSTTRANSISTOR SO AS TO PROVIDE FOR BISTABLE OPERATION OF SAID CIRCUIT MEANSIN RESPONSE TO THE SIGNAL INDUCED IN SAID OUTPUT WINDING AS A RESULT OFTHE SWITCHING OF SAID CORE, A LOAD IMPEDANCE MEANS, A DIODE COUPLED TOTHE COLLECTOR OF ONE OF SAID TRANSISTORS, AND MEANS COUPLING SAIDINHIBITING WINDING BETWEEN SAID LOAD IMPEDANCE MEANS AND SAID DIODE,SAID DIODE BEING POLED IN THE DIRECTION OF INHIBIT CURRENT FLOW.